Memory device, host device, memory system, memory device control method, host device control method and memory system control method

ABSTRACT

A memory card  100  having a NAND type flash memory connectable to a host device  200,  capable of transmitting/receiving a signal to/from the host device  200  at a first voltage (3.3 V) or a second voltage (1.8 V) and safely changing a signal voltage of a transmission/reception signal that mutually checks a signal voltage through handshake processing with the host device  200  when the signal voltage is switched.

CROSS-REFERENCE TO RELATED APPLICATIONS

This applicationMore than one reissue application has been filed for thereissue of U.S. Pat. No 9,383,792. This application is a continuationreissue of application Ser. No. 17/135,608, filed Dec. 28, 2020, whichis a continuation reissue of application Ser. No. 16/249,093, filed Jan.16, 2019, now RE48,418, which is a continuation reissue of applicationSer. No. 15/463,738, filed Mar. 20, 2017, now U.S. Pat. No. RE47,308,which is a reissue of application Ser. No. 14/312,543, filed Jun. 23,2014, now U.S. Pat. No. 9,383,792, which is a continuation of and claimsthe benefit of priority under 35 U.S.C. § 120 from U.S. Ser. No.13/667,285, filed Nov. 2, 2012, now U.S. Pat. No. 8,799,689, which is acontinuation of U.S. Ser. No. 12/933,586, filed Sep. 20, 2010, now U.S.Pat. No. 8,321,697, which is a National Stage of PCT/JP2008/066618,filed on Sep. 9, 2008, and claims the benefit of priority from JP2008-072429 filed Mar. 19, 2008 and JP 2008-099740 filed Apr. 7, 2008,the entire contents of each of which are incorporated herein byreference.

TECHNICAL FIELD

The present invention relates to a memory device including asemiconductor memory section, a host device, a memory system, a memorydevice control method, a host device control method and a memory systemcontrol method, and more particularly, to a memory device or the likecapable of changing a voltage of a data transfer signal.

BACKGROUND ART

In recent years, semiconductor storage devices, for example, flashmemory cards, which are non-volatile semiconductor storage media, havebeen developed and are widely used as external storage devices forinformation devices such as a digital camera which is a host device.Accompanying an increasing volume of data handled by host devices,volume and density of flash memories are also being increased.

A NAND type flash memory is a flash memory featuring a large volume andwidely used particularly for applications such as file memories inrecent years.

The NAND type flash memory uses electric charge injected into a traplayer made up of a floating gate or multi-layered film via a tunnelinsulating film, in other words, a charge accumulated layer as digitalbit information according to the amount of electric charge and reads thedigital hit information as two-valued or multi-valued information.Unlike destructive reading type memory such as DRAM, the NAND type flashmemory can read data without corrupting data.

Semiconductor storage devices are required to realize higher-speedwriting and reading and also required to increase the bus transfer rateof a transfer bus. For this reason, for example, a high-speed modespecification with the transfer clock frequency of a memory card busincreased from 25 MHz in a normal mode to 50 MHz is defined allowingfast data transfers.

On the other hand, Japanese Patent Application Laid-Open Publication No.2007-11788 discloses a memory card, for faster data transfer, thatprovides an ultra-high-speed mode capable of achieving a double datatransfer rate at the same clock frequency as that of a high-speed modeby transmitting/receiving data in synchronization with the rising edgeand falling edge of a clock signal supplied from a host device.

However, increasing the transfer clock frequency raises a problem ofshielding unnecessary radiation electromagnetic wave, that is, takingremedial actions for EMI (Electro Magnetic Susceptibility). Furthermore,increasing the transfer clock frequency also results in a problem thatpower consumption of the memory card increases.

To solve these problems, it is effective to reduce signal voltages oftransmission/reception signals between the memory card and a hostdevice. However, when the signal voltage of a transmission/receptionsignal is changed, a voltage higher than expected is applied, increasinga possibility that an I/O cell of the memory card or host device may bedestroyed.

DISCLOSURE OF INVENTION Means for Solving the Problem

An embodiment of the present invention provides a memory deviceconnectable to a host device including: a non-volatile memory section; afirst I/O cell that can transmit and receive a command signal, aresponse signal, a clock signal or a data signal to/from the host devicethrough a command signal line, a response signal line, a clock signalline or a data signal line respectively at any one signal voltageselected from a first voltage and a second voltage which is lower thanthe first voltage; a first regulator that can output the first voltageand the second voltage; and a memory controller that sends, uponreceiving the command signal requesting the signal voltage to beswitched from the first voltage to the second voltage from the hostdevice, information indicating that the signal voltage will be switchedto the host device using a response signal, switches the voltageoutputted from the first regulator from the first voltage to the secondvoltage applies, upon detecting that a voltage other than a ground levelis applied to the clock signal line after a lapse of a predeterminedtime, a second voltage to the response signal line and data signal lineof the ground level and starts transmission/reception at the signalvoltage of the second voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view showing a configuration of a memory systemmade up of a memory card and a host device according to an embodiment;

FIG. 2 is a block diagram showing a configuration of a power circuitpart of the memory system according to the embodiment;

FIG. 3A is a flowchart illustrating a signal voltage switching operationin the memory system according to the embodiment;

FIG. 3B is a flowchart illustrating the signal voltage switchingoperation in the memory system according to the embodiment;

FIG. 4 is a bus timing chart during the signal voltage switchingoperation in the memory system according to the embodiment;

FIG. 5 is a bus timing chart during the signal voltage switchingoperation in the memory system according to the embodiment;

FIG. 6 is a partial configuration diagram showing a partialconfiguration of I/O cells of the memory card and host device accordingto the embodiment;

FIG. 7A is a diagram illustrating parameter examples of a switch commandsent by the host device according to the embodiment;

FIG. 7B is a diagram illustrating parameter examples of a switch commandsent by the host device according to the embodiment;

FIG. 8A is a flowchart illustrating a signal voltage switching operationin a memory system according to a second embodiment;

FIG. 8B is a flowchart illustrating the signal voltage switchingoperation in the memory system according to the second embodiment;

FIG. 9 is a bus timing chart during a signal voltage switching operationin the memory system according to the second embodiment; and

FIG. 10 is another bus timing chart during the signal voltage switchingoperation in the memory system according to the second embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment

Hereinafter, a memory card 100 which is a memory device, a host device200, and a memory system 1 provided with the memory card 100 and thehost device 200 according to a first embodiment of the present inventionwill be explained with reference to the accompanying drawings.

FIG. 1 is a schematic view showing a configuration of the memory system1 made up of the memory card 100 and the host device 200 and FIG. 2 is ablock diagram showing a configuration of a power circuit part of thememory system 1.

As shown in FIG. 1 , the memory card 100 is connectable to the hostdevice 200 and is an SD memory card (registered trademark) connected tothe host device 200 and used as an external storage device of the hostdevice 200. Examples of the host device 200 include an informationprocessing apparatus including a personal computer that processesvarious kinds of data such as image data or music data, and a digitalcamera. The host device 200 includes an I/O cell 209 fortransmitting/receiving a command signal, response signal, clock signaland data signal, that is, transmission signals to/from the memory card100 connected and a host control section 251 that controlstransmission/reception of a transmission signal or the like.

The memory card 100 is provided with a memory section 150 made up of anon-volatile memory, a memory controller 151 that controls the memorysection 150 and transmission/reception or the like of a transmissionsignal, an I/O cell 121 for inputting/outputting data and a connector152 (including pin 1 to pin 9). The memory controller 151 is connectedto the memory section 150 via a bus of, for example, 8-bit bus width.

When the memory card 100 is attached to the host device 200, theconnector 152 is electrically connected to the host device 200.Allocation of signal lines to the pin 1 to pin 9 included in theconnector 152 is defined in the standard of an SD memory card(registered trademark).

That is, data DAT0, DAT1, DAT2 and DAT3 to transmit and receive a datasignal are allocated to pin 7, pin 8, pin 9 and pin 1 respectively.Furthermore, the pin 1 is also allocated to a card detection signal CD.A command signal CMD and a response signal RES which is a responsesignal of the memory card 100 to this command signal are allocated tothe pin 2. A clock signal CLK is allocated to the pin 5. A supplyvoltage VDD is allocated to the pin 4 and a grounding voltage VSS1 isallocated to the pin 3 and a grounding voltage VSS2 is allocated to thepin 6.

In the memory card 100 of the present embodiment, the memory section 150is a non-volatile semiconductor memory and made up of a NAND type flashmemory. Data or the like sent from the host device 200 is stored in thememory section 150.

Furthermore, as shown in FIG, 2, the bus that transmits/receives asignal or the like between the memory card 100 and host device 200includes a CLK line 111 (hereinafter also referred to as a “clock signalline”), a CMD/RES line 112 (hereinafter also referred to as a “CMDline”), a DAT[3:0] line 113 and a VDD line (hereinafter also referred toas a “power line”), and a DAT1 line, a DAT2 line, a CD/DAT3 line, a VSS1line and a VSS2 line which are not shown. Hereinafter, the DAT0 line(hereinafter also referred to as a “data line”) will be explained as anexample of the data signal line. Furthermore, the CMD/RES line is alsoreferred to as a command signal line or response signal (RES) line. Thatis, the command signal line and the response signal line are one and thesame signal line.

As the operation mode (hereinafter also referred to as a “transfermode”) of the memory card 100 which is the SD memory card (registeredtrademark) during a data transfer, an SD mode and an SPI mode aredefined. Furthermore, as the transfer mode of the SD mode, two modes: a1-bit mode using only the data DAT0 and a 4-bit mode using the data DAT0to DAT3 are defined. As the transfer mode of the memory card 100, inaddition to a normal speed mode (NSM) of a normal transfer rate and ahigh-speed mode (HSM) of a speed doubling that of the NSM, anultra-high-speed mode (UHSM) of a speed further doubling that of the HSPis defined depending on the transfer clock frequency or the like,

As shown in FIG. 2 , the memory card 100 of the memory system 1 has aregulator (VR2) 116, which is a first regulator, and the host device 200of the memory system 1 has a regulator (VR1) 204 which is a secondregulator. Therefore, in addition to a data transfer mode whose signalvoltage is a standard 3.3 V (hereinafter referred to as a “3.3 V mode”)which is a voltage mode supported by many memory systems 1, the memorysystem 1 supports a mode in which the supply voltage remains standard3.3 V and the data transfer signal voltage is set to a lower voltage 1.8V (hereinafter referred to as a “1.8 V mode”).

That is, the memory card 100 has a multi-drive type first I/O cell 121that can transmit and receive a command signal, response signal, clocksignal and data signal to/from the host device 200 at any one signalvoltage selected from a first voltage (3.3 V) and a second voltage (1.8V), which is lower than the first voltage and the first regulator 116that can output the first voltage and the second voltage, and the hostdevice 200 has a multi-drive type second I/O cell 209 and the secondregulator 204 of specifications similar to those of the memory card 100.

In FIG. 2 , a power switch (PSW) 201 is a switch that turns ON/OFF thesupply voltage (VDD) applied to the memory card 100. Band gap references(BGR) 115 and 203 are reference voltage generation circuits using apotential difference of a band gap. Noise filters (Filter) 114 and 201are not indispensable parts, yet effective in preventing noise from thepower line (VDD) and generating more stable reference voltages. Thefirst regulator (VR2) 116 and the second regulator (VR1) 204 areregulators that create a 1.8 V voltage from a 3.3 V supply voltage andgenerate the 1.8 V voltage based on the reference voltages of the BGRs115 and 203 respectively.

A third regulator (VR3) 122 which is a core voltage generation circuit,which is an internal logic circuit, generates a voltage supplied to arandom logic section 123. The random logic section 123 is a circuithaving the memory controller 151 shown in FIG. 1 , ROM and RAM or thelike. The host device 200 may also need a voltage generation circuit forthe internal logic, which is however not shown. A comparator (VDCLK)120, which is a first voltage comparison circuit, detects whether or notthe voltage of the CLK line is 1.8 V. Furthermore, a comparator(VDCMD/RES) 208, which is a second voltage comparison circuit, detectswhether or not the voltage of the CMD/RES line is 1.8 V. On the otherhand, a comparator 119, which is a third voltage comparison circuit or acomparator 207, which is a fourth voltage comparison circuit, detectswhether or not a 1.8 V voltage is correctly generated from the firstregulator (VR2) 116 or the second regulator (VR1) 204 respectively.

Here, that the second voltage is 1.8 V means that the second voltagefalls within a range of 1.65 V to 1.95 V. Furthermore, the comparatorthat detects whether a voltage is the first voltage or the secondvoltage is a voltage comparator having a third threshold voltageintermediate between the first voltage and the second voltage, decideson the first voltage when the voltage of the measurement line is higherthan the third threshold voltage, and decides on the second voltage whenthe voltage of the measurement line is lower than the third thresholdvoltage.

When the signal of the bus line is a tri-state, pull-up resistors 224and 225 keep the voltage of each line to 3.3 V or 1.8 V. Furthermore,capacitors 118 and 206 accumulate charge to stabilize a predeterminedvoltage.

Next, a signal voltage switching operation of the memory system 1 willbe explained using FIG. 3A, FIG. 3B and FIG. 4 . FIG. 3A and FIG. 3B areflowcharts illustrating the signal voltage switching operation of thememory system 1 and FIG. 4 is a timing chart of a signal line group(bus) during the signal voltage switching operation of the memory system1.

The host device 200 performs a signal voltage switching operation takinginto consideration compatibility with the memory card supporting onlythe 3.3 V mode. That is, if the host device 200 applies a 1.8 V signalvoltage to the connected memory card from the beginning, the input I/Ocell of the memory card supporting only the 3.3 V mode recognizes theapplied 1.8 V as an intermediate voltage. Therefore, a large throughcurrent may flow through the input I/O cell of the memory card.

Therefore, the host device 200 follows a procedure of sending a signalof 3.3 V signal voltage to the memory card first and switching to the1.8 V mode only after detecting that the memory card is a memory cardthat supports the 1.8 V mode through handshake processing which will bedescribed later.

Hereinafter, the signal voltage switching operation of the memory system1 will be explained following the flowcharts in FIG. 3A and FIG. 3B. Theleft side of FIG. 3A and FIG. 3B shows the operation flow of the hostdevice 200 and the right side shows the operation flow of the memorycard 100.

<Step S10> Memory Card Connected to Host Device

The memory card 100 is connected to the host device 200. That is, withthe lines 111 to 113 making up the bus interface, the I/O cell 121 ofthe memory card 100 and the I/O cell 209 of the host device 200 areconnected through the command/response signal line, clock signal lineand data signal line or the like.

<Step S11> CMD8

In the case of the host device 200 supporting a 1.8 V mode, the hostdevice 200 inquires whether or not the connected memory card 100supports the 1.8 V mode. That is, the host device 200 issues a commandCMD8 first (FIG. 4 : T1). Since a bit requesting the shift to the 1.8 Vmode is set in an argument of the CMD8, the command signal CMD8transmitted from this host device 200 to the memory card 100 is also acommand signal that informs that the signal voltage will be changed fromthe first voltage (3.3 V) to the second voltage (1.8 V).

<Step S12> 1.8 V supported?

Upon receiving the command signal CMD8 from the host device, the memorycard 100 decides whether or not the memory card 100 supports the 1.8 Vmode.

<Step S13> RES 1.8 V Not Supported/RES 1.8 V Supported

When the memory card 100 does not support the 1.8 V mode (step S12: No),the memory card 100 sends in reply a response signal indicating that the1.8 V mode is not supported to the host device 200.

On the other hand, when the memory card 100 supports the 1.8 V mode(step S12: Yes), the memory card 100 sends in reply a response signalindicating that the mode will be switched to the 1.8 V mode to the hostdevice 200 (FIG. 4 : T2).

<Step S14> 1.8 V Supported?

Upon receiving a response signal (No) indicating that the 1.8 V mode isnot supported from the memory card 100, the host device 200 startsinitialization processing in the 3.3 V mode in S33.

On the other hand, upon receiving a response signal (Yes) indicatingthat the 1.8 V mode is supported from the memory card 100, the hostdevice 200 performs processing of mutually sending a next transmissionsignal based on the contents of the received signal, so-called handshakeprocessing.

<Step S15> Drive CMD/RES to 0 V

After sending the response signal, the memory card 100 sets the CMD lineto L level (ground level=0 V) (FIG. 4 : T3).

<Step S16> Stop CLK to 0 V, Drive DAT to 0 V

The host device 200 sets the DAT line to L level (ground level: 0 V)(FIG. 4 : T4), stops clock oscillation and also sets the CLK line to Llevel (ground level: 0 V) (FIG. 4 : T5). Any line of the DAT line andCLK line can be driven to L level first.

Here, the reason that the CMD line, CLK line and DAT line are set, thatis, driven to L level (0 V) is to prevent the respective lines frombecoming a tri-state and prevent unstable voltages from being applied.When all unstable voltage is applied to the I/O cell 121 or the like fora voltage switching period, there is a danger that a through current mayflow through the I/O cell 121 or the like. For this reason, the hostdevice 200 or memory card 100 fixes the voltage of the signal line to Llevel (0 V).

<Step S17, step S18> VR1, VR2 from 3.3 V to 1.8 V

The memory card 100 switches the regulator VR2 so as to generate 1.8 V.Furthermore, the host device 200 switches the regulator VR1 so as togenerate 1.8 V.

<Step S19, step S20> Timer Set

The host device 200 waits until a predetermined time elapses (FIG. 4 :T5 to T6). Therefore, the timer sets 100 microseconds for example.

This is because the host device 200 needs to wait for the capacitors 206and 118 connected to the regulator VR1 and regulator VR2 respectively todischarge from a state charged to 3.3 V to a state charged to 1.8 V.

It is of course possible to provide a circuit that causes the capacitors206 and 118 to actively discharge, but since the discharge time is asufficiently short time to human senses, the memory system 1 is notprovided with any discharge circuit. The above described explanationassumes that the waiting time is 100 microseconds, but the waiting timevaries depending on the specification of the capacitor 206 or 118 and isgenerally on the order of 10 to 500 microseconds.<Step S21> Drive CLK to 1.8 V-DC

The host device 200 sets the clock signal line at the ground level to1.8 V for a predetermined time after a lapse of 100 microseconds in theabove described example (FIG. 4 : T6). Here, the host device 200 appliesa 1.8 V DC signal to the clock signal line which normally sends a clocksignal. The host device 200 then informs the memory card 100 that the1.8 V signal voltage can be supplied from the regulator VR2.

<Step S22> CLK 1.8 V?

When a voltage is applied to the clock signal line, the memory card 100checks with the comparator 120, which is the first voltage comparisoncircuit, whether or not the signal voltage is 1.8 V. When no 1.8 Vvoltage is applied to the clock signal line (No), the memory card 100does not perform further voltage switching processing and the memorycard 100 stops operating in step S32.

<Step S23> Drive CMD/RES to 1.8 V-DC

In step S22, when the signal voltage of the clock signal line isconfirmed to be 1.8 V (Yes), the memory card 100 drives the CMD/RES line(response signal line) at the ground level to 1.8 V (FIG. 4 : T7). Here,the memory card 100 applies a 1.8 V DC signal to the response signalline which normally sends a RES signal.

<Step S24> Timer Set

After setting the signal voltage of the clock signal line to 1.8 V, thehost device sets the timer.

<Step S25> CMD Line 1.8 V?

When a voltage is applied to the CMD/RES line, the host device 200detects with the comparator (VDCMD/RES) 208 which is the second voltagecomparison circuit whether or not the signal voltage of the CMD/RESsignal line is 1.8 V.

<Step S26, Step S27>

When the 1.8 V voltage has not been applied to the clock signal line(No) even after a lapse of a predetermined time, for example, 100microseconds, the host device 200 turns OFF the power switch (PSW) 201in step S27 and stops the operation of the memory card 100.

As explained above, when the memory card 100 or the host device 200 doesnot perform the predetermined operation even after a lapse of thepredetermined time in the middle of handshake processing in the voltageswitching processing, the memory system 1 of the present embodiment maydetect that switching to 1.8 V has not been successfully performed andthereby output an error code or execute initialization processing in a3.3 V mode. An example thereof will be shown in FIG. 5 .

FIG. 5 shows a timing chart when the memory card 100 has not driven theCMD/RES line (response signal line) to 1.8 V in step S23. The hostdevice 200 applies a 1.8 V voltage to the clock signal line and waitsfor a response operation from the memory card 100, that is, for theresponse signal line to change from 0 V (ground level) to 1.8 V.However, when the response signal line does not become 1.8 V even aftera lapse of a predetermined time (for example, 100 microseconds), thehost device 200 turns OFF the power switch 201 at T12 and stops thesupply voltage (VDD) applied to the memory card 100. Furthermore, thehost device 200 sets the voltage of the CLK signal line to 0 V.

Not only in the case shown in FIG. 5 , but also in the event of an errorin the middle of handshake processing during the voltage switchingprocessing, the host device 200 sets the voltage of the CLK signal lineto 0 V and stops the power supply to the memory card 100.

<Step S28> CLK Oscillation

In step S24, when the signal voltage of the CMD/RES signal line isconfirmed to be 1.8 V (Yes), the host device 200 sends an oscillatingclock signal to the clock signal line, in other words, oscillates theclock signal (FIG. 4 : T8).

<Step S29, Step 30> Drive DAT to 1.8 V/DAT to Tri-State

After clock oscillation starts, the host device 200 drives the DATsignal line to a 1.8 V voltage for a short time (FIGS. 4 : T9 to T10),sets the DAT signal line to a tri-state. Since the DAT signal line ispulled up at 1.8 V, the voltage level of 1.8 V is maintained.

<Step S31, Step 32> CLK Oscillated?/CMD/RES to Tri-State

Upon receiving the oscillating clock signal from the host device 200(Yes), the memory card 100 sets the CMD/RES line to a tri-state in stepS29 (FIG. 4 : T11). Since the CMD/RES line is pulled up at 1.8 V, the1.8 V voltage level is maintained.

When the oscillating clock signal is not applied to the clock signalline (No), the memory card 100 stops operating in step S35.

<Step S33>

Both the memory card 100 and host device 200 perform initializationprocessing in the 3.3 V mode and transmits/receives subsequent signalsat a 3.3 V signal voltage.

<Step S34>

Both the memory card 100 and host device 200 complete the processing ofmoving to the 1.8 V mode and transmits/receives subsequent signals at a1.8 V signal voltage.

<Step S35>

When the procedure for moving the signal voltage to the 1.8 V mode failsand the memory card 100 stops, the host device 200 turns OFF once thepower and then sends the 3.3 V signal voltage to the memory card 100again and performs initialization processing in the 3.3 V mode withoutswitching to the 1.8 V mode.

As explained above, in the memory system 1, the memory card 100 and hostdevice 200 mutually check signal voltages used through handshakeprocessing and thereby prevent the I/O cell or the like from beingdamaged. Furthermore, in the memory system 1, the memory card 100 andhost device 200 mutually check the voltage of the output of theregulator 116 or 204, and can thereby improve the reliability of thevoltage applied to the signal line. Furthermore, the memory system 1defines the handshake processing sequence using the clock signal lineand command signal line, and can thereby follow a procedure to safelyperform switching from the first voltage (3.3 V) to the second voltage(1.8 V).

Even with the memory system 1, it remains possible to cause the I/O cell121 or 209 damaged if switching to the 1.8 V mode is frequentlyperformed. Therefore, the memory system 1 can preferably perform normalprocessing of switching the signal voltage to the 1.8 V mode only at thefirst stage before the initialization processing starts. That is, afterswitching to the 1.8 V mode, the memory system 1 does not change thevoltage mode even if a reset command is issued.

In other words, even when a reset command is issued, the memory card 100and host device 200 transmit and receive all signals at the secondvoltage of 1.8 V, and this state continues until the operation of thememory system 1 is completed where the supply voltage becomes 0 V.

Since the memory system 1 should not frequently switch the voltage mode,it is possible to maintain stability and reliability by preventing thesignal voltage from being changed even by a reset.

Next, a protection diode owned by the memory card 100 and host device200 will be explained using FIG. 6 . FIG. 6 is a partial configurationdiagram showing partial configurations of the I/O cells 121 and 209 ofthe memory card 100 and host device 200.

Any one voltage of 3.3 V and 1.8 V which are the outputs of theregulators 204 and 116 is selected and applied to the I/O cells 209 and121 of the host device 200 and memory card 100 respectively. Therefore,when the voltage is switched, there may be a time during which theoutput voltage of the regulator 204 differs from that of the regulator116. When the output voltage of the regulator 204 is different from thatof the regulator 116, a current may flow through an unexpected path anddamage the I/O cell 121 or 209 or the like.

In the host device 200 and the memory card 100, protection diodes 232and 136 are connected to the power lines of a 3.3 V voltage. Therefore,in the host device 200 and memory card 100, a protection diode 137 or233 is not damaged by an applied voltage exceeding 1.8 V even in the 1.8V mode.

That is, the memory card 100 has the non-volatile memory section 150which is connectable to the host device 200, the power line VDD 114 thatsupplies the first voltage (3.3 V), the first regulator 116 that canoutput power of any one voltage selected from the first voltage (3.3 V)and the second voltage (1.8 V) which is lower than the first voltagefrom the VDD 114, the I/O cell 121 that receives the power supply fromthe first regulator 116 and transmits/receives signals to/from the hostdevice 200, and the protection diode 136 connected to an input end ofthe I/O cell 121 and an end of the power supply connected to the 3.3 Vpower line to protect the I/O cell 121 from an overvoltage, wherein itis possible to perform transmission/reception to/from the host device200 with a signal of any one voltage selected from the first voltage(3.3 V) and second voltage (1.8 V).

In the memory system 1, both the host device 200 and memory card 100have the regulator 116 or 204 that can output two voltages, andtherefore connecting the protection diode to the regulator output maydamage the protection diode. When the signal voltage is set to 1.8 V,the supply voltage itself is generally set to 1.8 V, but sincecompatibility is taken into consideration in the memory system 1, thesupply voltage is set to 3.3 V. Therefore, the above describedprotection diode 136 is effective in preventing damage to the protectiondiode in the memory system 1.

As explained above, the host device 200 and the memory card 100 switchthe voltage mode only at the stage of connection start. Therefore, thehost device 200 never switches voltages by sending a switch command FIG.7A and FIG. 7B are diagrams illustrating parameter examples of a switchcommand for changing the transfer mode in which the host device 200performs transmission.

The present embodiment has explained the memory system 1 or the likehaving an SD memory card (registered trademark) as the memory device foran example, but the present embodiment is also applicable to a memorysystem having another memory card, memory device, inner memory or thelike as long as the memory system has a similar bus structure and canexert operations and effects similar to those of the memory system 1 orthe like.

As described above, the memory device or the like of the presentinvention is as follows.

1. A memory device, host device, memory system, memory device controlmethod, host device control method and memory system control method.

2. The memory device according to 1 above, wherein the memory deviceincludes a memory controller and upon sending the response signalindicating that the signal voltage is switched from the first voltage tothe second voltage, the memory controller holds a response signal lineto 0 V.3. The memory device according to 1 or 2 above, wherein the host deviceincludes a host control section and upon receiving through the responsesignal that the signal voltage is switched from the first voltage to thesecond voltage, the host control section stops the clock signal andholds the clock signal line and the data signal line to 0 V.4. The memory device according to any one of 1 to 3 above, whereinvoltages detected by the first voltage comparison circuit and the secondvoltage comparison circuit are voltages of DC currents.5. The memory device according to any one of I to 4 above, wherein thememory controller and the host control section wait for a predeterminedtime after starting to switch voltages outputted from the firstregulator and the second regulator from the first voltage to the secondvoltage.6. The memory device according to any one of 1 to 5 above, furtherincluding a third voltage comparison circuit and a fourth voltagecomparison circuit that detect that the voltages outputted by the firstregulator and the second regulator are the second voltages.7. The memory device according to any one of 1 to 6 above, wherein thefirst I/O cell and the second I/O cell include protection diodes thatprotect the respective I/O cells from an overvoltage.8. The memory device according to any one of 1 to 7 above, wherein afterswitching the signal voltage from the first voltage to the secondvoltage, the memory controller and the host control section transmit andreceive the signal at the second voltage until the power is turned OFF.9. The memory device according to any one of 1 to 8 above, wherein thememory section is a NAND type flash memory.

Furthermore, the memory device or the like of the present invention is amemory system having the memory device according to 2 to 8 above, amethod of controlling the memory device and a method of controlling thememory system according to 2 to 8 above.

Furthermore, the memory device, host device, memory system, memorydevice control method, host device control method and memory systemcontrol method of the present embodiment will be described hereinafter.

1. A memory device connectable to a host device, the memory deviceincluding a non-volatile memory section, a first I/O cell that cantransmit and receive a command signal, response signal, clock signal anddata signal to/from the host device via a command signal line, responsesignal line, clock signal line or data signal line respectively at anyone signal voltage selected from a first voltage and a second voltagewhich is lower than the first voltage, a first regulator that can outputthe first voltage and the second voltage, and a memory controller thatsends, upon receiving the command signal requesting switching of thesignal voltage from the first voltage to the second voltage from thehost device, information indicating that the signal voltage will beswitched to the host device using the response signal, switches avoltage outputted by the first regulator from the first voltage to thesecond voltage, applies, upon detecting that a clock signal line is atthe second voltage, the second voltage to the response signal line at aground level and starts, upon detecting oscillation of the clock signal,to transmit and receive a signal voltage of the second voltage.2. The memory device according to 1 above, further including a firstvoltage comparison circuit that detects that a signal voltage of theclock signal line is the second voltage.3. A host device to which a memory device having a non-volatile memorysection is connectable, the host device including a second I/O cell thatcan transmit and receive a command signal, response signal, clock signaland data signal to/from the memory device via a command signal line,response signal line, clock signal line or data signal line respectivelyat any one signal voltage selected from a first voltage and a secondvoltage which is lower than the first voltage, a second regulator thatcan output the first voltage and the second voltage, and a host controlsection that sends, when the signal voltage is switched from the firstvoltage to the second voltage, information indicating that the signalvoltage will be switched using the command signal, switches, uponreceiving the response signal indicating that the signal voltage can beswitched, a voltage outputted by the second regulator from the firstvoltage to the second voltage, applies the second voltage to the clocksignal line at a ground level, oscillates, upon detecting that theresponse signal line is at the second voltage, the clock signal andstarts transmission/reception at a signal voltage of the second voltage.4. A host device to which a memory device having a non-volatile memorysection is connectable, the host device including a second I/O cell thatcan transmit and receive a command signal, response signal, clock signaland data signal to/from the memory device via a command signal line,response signal line, clock signal line or data signal line respectivelyat any one signal voltage selected from a first voltage and a secondvoltage which is lower than the first voltage, a second regulator thatcan output the first voltage and the second voltage, and a host controlsection that sends, when the signal voltage is switched from the firstvoltage to the second voltage, information indicating that the signalvoltage will be switched using the command signal, turns OFF once thepower of the memory device when the response signal indicating that thesignal voltage can be switched cannot be received for a predeterminedtime or upon receiving a response signal indicating that switching isnot possible and starts transmission/reception at the first voltageagain.5. The host device according to 3 or 4 above, further including a secondvoltage comparison circuit that detects that a signal voltage of theresponse signal line is the second voltage.6. A memory system including a memory device including a first I/O cellthat can transmit and receive a command signal, response signal, clocksignal and data signal to/from the host device via a command signalline, response signal line, clock signal line or data signal linerespectively at any one signal voltage selected from a first voltage anda second voltage which is lower than the first voltage, a firstregulator that can output the first voltage and the second voltage, anda memory controller that receives the command signal that requestsswitching of the signal voltage from the host device including a secondI/O cell that can perform transmission/reception to/from the memorydevice when the signal voltage is switched from the first voltage to thesecond voltage at any one signal voltage selected from the first voltageand the second voltage and a second regulator that can output the firstvoltage and the second voltage, sends information indicating that thesignal voltage can be switched to the host device using the responsesignal at the first voltage, switches a voltage outputted by the firstregulator from the first voltage to the second voltage, applies, upondetecting that the clock signal line is at the second voltage, thesecond voltage to the response signal line at a ground level and startstransmission/reception upon detecting that the response signal line isat the second voltage and detecting oscillation of a clock signal fromthe host device at a signal voltage of the second voltage, and a hostdevice including a second I/O cell that can performtransmission/reception to/from the memory device at any one signalvoltage selected from the first voltage and the second voltage, a secondregulator that can output the first voltage and the second voltage, anda host control section that sends, when the signal voltage is switchedfrom the first voltage to the second voltage, the command signalrequesting switching of the signal voltage to the memory device,receives information indicating that the signal voltage can be switchedfrom the memory device using the response signal at the first voltage,switches a voltage outputted by the second regulator from the firstvoltage to the second voltage, applies the second voltage to a clocksignal line at a ground level and oscillates the clock signal upondetecting that the response signal line is at the second voltage.7. The memory system according to 6 above, wherein the memory devicefurther includes a first voltage comparison circuit that detects that asignal voltage of the clock signal line is the second voltage and thehost device further includes a second voltage comparison circuit thatdetects that a signal voltage of the response signal line is the secondvoltage.8. A method of controlling a memory device connectable to a host device,the memory device including a non-volatile memory section, a first I/Ocell that can transmit and receive a command signal, response signal,clock signal and data signal to/from the host device via a commandsignal line, response signal line, clock signal line or data signal lineat any one signal voltage selected from a first voltage and a secondvoltage which is lower than the first voltage, a first regulator thatcan output the first voltage and the second voltage and a memorycontroller, the method including a command receiving step of receivingthe command signal requesting switching of the signal voltage from thefirst voltage to the second voltage from the host device, a responsesignal sending step of sending information indicating that the signalvoltage can be switched to the host device using the response signal, afirst regulator switching step of switching a voltage outputted by thefirst regulator from the first voltage to the second voltage, a clocksignal line voltage detecting step of detecting that the clock signalline is at the second voltage, a response signal line voltage applyingstep of applying the second voltage to the response signal line at aground level, a clock signal oscillation detecting step of detectingoscillation of the clock signal and a transmitting/receiving step ofstarting transmission/reception at a signal voltage of the secondvoltage.9. The method of controlling a memory device according to 8 above, thememory device further including a first voltage comparison circuit thatdetects that a signal voltage of the clock signal line is the secondvoltage.10. A method of controlling a host device to which a memory devicehaving a non-volatile memory section is connectable, the host deviceincluding a second I/O cell that can transmit and receive a commandsignal, response signal, clock signal and data signal to/from the memorydevice via a command signal line, response signal line, clock signalline or data signal line respectively at any one signal voltage selectedfrom a first voltage and a second voltage which is lower than the firstvoltage and a second regulator that can output the first voltage and thesecond voltage and a host control section, the method including acommand signal sending step of sending, when the signal voltage isswitched from the first voltage to the second voltage, informationindicating that the signal voltage will be switched using the commandsignal, a response signal receiving step of receiving the responsesignal indicating that the signal voltage can be switched, a regulatorvoltage switching step of switching a voltage outputted by the secondregulator from the first voltage to the second voltage, a clock signalline voltage applying step of applying the second voltage to the clocksignal line at a ground level, a response signal line voltage detectingstep of detecting that the response signal line is at the secondvoltage, a clock signal oscillation step of oscillating the clock signaland a transmitting/receiving step of starting transmission/reception ata signal voltage of the second voltage.11. The method of controlling a host device according to 10 above, thehost device further including a second voltage comparison circuit thatdetects that a signal voltage of the response signal line is the secondvoltage.12. A method of controlling a memory system including a host device anda memory device connectable to the host device, when the memory deviceincluding a non-volatile memory section, a first I/O cell that cantransmit and receive a command signal, response signal, clock signal anddata signal to/from the host device via a command signal line, responsesignal line, clock signal line or data signal line respectively at anyone signal voltage selected from the first voltage and a second voltagewhich is lower than the first voltage, a first regulator that can outputthe first voltage and the second voltage and a memory controller, andthe host device including a second I/O cell that can transmit andreceive the signal to/from the memory device at the signal voltageselected from the first voltage and the second voltage, a secondregulator that can output the first voltage and the second voltage and ahost control section switch the signal voltage from the first voltage tothe second voltage, the method including a command signal sending stepof sending the command signal requesting switching of the signal voltageto the memory device, a response signal sending step of the memorydevice sending information indicating that the signal voltage can beswitched to the host device using the response signal at the firstvoltage, a regulator voltage switching step of the memory device and thehost device switching a voltage outputted by the first regulator and thesecond regulator from the first voltage to the second voltage, a clocksignal line voltage applying step of the host device applying the secondvoltage to the clock signal line at a ground level, a clock signal linevoltage detecting step of the memory device detecting that the clocksignal line is at the second voltage, a response signal line voltageapplying step of the memory device applying the second voltage to theresponse signal line at a ground level, a response signal line voltagedetecting step of the host device detecting that the response signalline is at the second voltage, a clock signal oscillation step of thehost device oscillating the clock signal, a clock signal oscillationdetecting step of the memory device detecting oscillation of the clocksignal, and a transmitting/receiving step of the memory device and thehost device starting transmission/reception at a signal voltage of thesecond voltage.13. The method of controlling a memory system according to 12 above,wherein the memory device includes a first voltage comparison circuitthat detects that a signal voltage of the clock signal line is thesecond voltage and the host device includes a second voltage comparisoncircuit that detects that a signal voltage of the response signal lineis the second voltage.14. A memory device connectable to a host device, including anon-volatile memory section, a memory controller, a power supply thatsupplies a first voltage, a regulator that can output power of any onevoltage selected from the first voltage and a second voltage which islower than the first voltage from the power supply, an I/O cell thatreceives a power supply from the regulator, can performtransmission/reception to/from the host device via a command signalline, response signal line, clock signal line or data signal linerespectively using a signal of any one voltage selected from the firstvoltage and the second voltage and a protection diode connected betweenan input end of the I/O cell and an end of the power supply to protectthe I/O cell from an overvoltage.15. A host device connectable to a memory device having a non-volatilememory section, including a host control section, a power supply thatsupplies a first voltage, a regulator that can output power of any onevoltage selected from the first voltage from the power supply and asecond voltage which is lower than the first voltage, an I/O cell thatreceives a power supply from the regulator, can performtransmission/reception to/from the memory device via a command signalline, response signal line, clock signal line or data signal line usinga signal at any one voltage selected from the first voltage and thesecond voltage and a protection diode connected between an input end ofthe I/O cell and an end of the power supply to protect the I/O cell froman overvoltage.

Second Embodiment

Hereinafter, a memory system 301 having a memory card 400 which is amemory device, a host device 500, a memory card 400 and a host device500 according to a second embodiment of the present invention will beexplained with reference to the accompanying drawings. Since the memorysystem 301 or the like of the present embodiment is similar to thememory system 1 or the like according to the first embodiment, the samecomponents will be assigned the same reference numerals and explanationsthereof will be omitted.

Next, a signal voltage switching operation of the memory system 301 willbe explained using FIG. 8A, FIG. 8B, FIG. 9 and FIG. 10 . FIG. 8A andFIG. 8B are flowcharts illustrating the signal voltage switchingoperation of the memory system 301 and FIG. 9 and FIG. 10 are timingcharts of a signal line group (bus) during the signal voltage switchingoperation of the memory system 301.

Hereinafter, the signal voltage switching operation of the memory system301 will be explained according to the flowcharts of FIG. 8A and FIG.8B. The left side of FIG. 8A and FIG. 8B shows an operation flow of thehost device 500 and the right side shows an operation flow of the memorycard 400.

<Step S40> to <Step S44>

Since these steps are the same as step S10 to step S14 of the memorysystem 1 or the like, explanations thereof will be omitted.

<Step S45> Drive CMD/RES to 0 V, Drive DAT to 0 V

After sending a response signal, the memory card 400 sets the CMD lineto L level (ground level: 0 V) (FIG. 9 : T3) and sets the DAT line to Llevel (ground level=0 V) (FIG. 9 : T4). Between the CMD/RES line and DATline, any line can be set to L level first.

<Step S46> Stop CLK to 0 V

The host device 500 stops clock oscillation and also sets the CLK lineto L level (ground level: 0 V) (FIG. 9 : T5).

<Step S47> to <Step S50>

Since these steps are the same as step S17 to step S20 of the memorysystem 1 or the like, explanations thereof will be omitted.

<Step S51> CLK Oscillation

After a lapse of a predetermined period (e.g., 100 microseconds) in thesteps 49, 50, the host device 500 sends an oscillating clock signal to aclock signal line, in other words, oscillates a clock signal (FIG. 9 :T6). The host device 500 then informs the memory card 400 that a 1.8 Vsignal voltage can be supplied from a regulator VR2.

<Step S52> CLK Oscillation?

The memory card 400 checks whether or not an H level clock signal of apredetermined voltage is applied to the clock signal line.

<Step S53>

This step is the same as step S23 of the memory system 1 or the like andtherefore explanations thereof will be omitted.

<Step S54> CMD/RES to Tri-State

The memory card 400 drives the CMD/RES line to a 1.8 V voltage for onlya short time (FIG. 9 : T7 to T8), and then sets the CMD/RES line to atri-state (FIG. 9 : T8). Since the CMD/RES line is pulled up at 1.8 V,the voltage level of 1.8 V is maintained.

<Step S55, Step 56> Drive DAT to 1.8 V/DAT to Tri-State

The memory card 400 drives the DAT signal line to a 1.8 V mode voltagefor only a short time (FIG. 9 : T9 to T10), then sets the DAT signalline to a tri-state. Since the DAT signal line is pulled up at 1.8 V,the voltage level of 1.8 V is maintained.

<Step S57> Clock Counter Set

The host device 500 sets the clock counter after oscillating the clocksignal and then sets a count n to 0.

<Step S58, Step S59>

The host device 500 waits until at least 16 clocks are counted. A valueequal to or greater than 16 clocks is set as the waiting time.

<Step S60> DAT Line 1.8 V?

The host device 500 detects that the DAT signal line is not at a groundlevel, that is, that a predetermined voltage is applied. Here, thepredetermined voltage is 1.8 V.

When no voltage is applied to the DAT signal line (No), the host device500 turns OFF a power switch (PSW) 201 in step S61 and stops operationof the memory card 400. When a voltage is applied to the DAT signal line(Yes), in step S63, the host device 500 transmits/receives subsequentsignals at a 1.8 V signal voltage.

Furthermore, the host device 500 detects that not only the DAT signalline but also the DAT signal line and CMD signal line are not at aground level, that is, by detecting that a predetermined voltage isapplied, it is possible to perform voltage switching processing moresafely. Here, the predetermined voltage is 1.8 V.

<Step S62>

Both the memory card 400 and the host device 500 perform initializationprocessing in a 3.3 V mode and transmits/receives subsequent signals ata 3.3 V signal voltage.

<Step S63>

Both the memory card 400 and the host device 500 complete the processingof moving to the 1.8 V mode and transmits/receives subsequent signals ata 1.8 V signal voltage.

When the procedure for moving to the 1.8 V mode signal voltage fails andthe memory card 400 stops, the host device 500 turns OFF once the power,sends a 3.3 V signal voltage to the memory card 400 again and performsinitialization processing in the 3.3 V mode without switching to the 1.8V mode.

As described above, the memory card 400 of the memory system 301 detectsthe voltage of the oscillation clock signal outputted by the host device500. This eliminates the necessity for a circuit that applies a DCvoltage to the clock signal line, which is required in the memory system1. Furthermore, the memory card 400 sets the DAT line to a tri-state.

Despite its simpler configuration, the memory system 301 of the presentembodiment can still exert effects similar to those of the memory system1 of the first embodiment.

Third Embodiment

Hereinafter, a memory card 700, which is a memory device, a host device800 and a memory system 601 having the memory card 700 and the hostdevice 800 according to a third embodiment of the present invention willbe explained. The memory system 601 or the like of the presentembodiment is similar to the memory system 301 or the like of the secondembodiment, and therefore the same components will be assigned the samereference numerals and explanations thereof will be omitted.

The memory system 601 or the like is not provided with the comparators119, 120, 207, 208 (see FIG. 2 ) for confirming that the voltage is adesired voltage, for example, 1.8 V.

Therefore, the memory card 700 checks in step S52 in FIG. 8A that theclock signal line is not at a ground level, that is, only thepresence/absence of clock oscillation. Furthermore, in step S55 in FIG.8B, the host device 800 only checks whether or not any voltage isapplied to the CMD line, that is, whether or not the CMD line is at aground level.

Despite its simpler configuration, the memory system 601 of the presentembodiment can still exert effects similar to those of the memory system1 or the like of the first embodiment.

Having described the preferred embodiments of the invention referring tothe accompanying drawings, it should be understood that the presentinvention is not limited to those precise embodiments and variouschanges and modifications thereof could be made by one skilled in theart without departing from the spirit or scope of the invention asdefined in the appended claims.

The present application is based on Japanese Patent Application No.2008-72429 filed on Mar. 19, 2008 and Japanese Patent Application No.2008-99740 filed on Apr. 7, 2008 as the basis for claiming priority,entire disclosure content of which is quoted in the specification of thepresent application, claims and drawings.

The invention claimed is:
 1. A connectable device connectable to a hostdevice comprising: a connectable interface that can receive a commandsignal via a command/response signal line, receive a clock signal via aclock signal line, transmit a response signal via the command/responsesignal line, and transmit and receive a data signal via data signallines at any one signal voltage selected from a first voltage and asecond voltage which is lower than the first voltage; a regulator thatcan output the first voltage and the second voltage; and a connectabledevice controller, the connectable device controller being configuredto: receive the command signal requesting switching of the signalvoltage from the first voltage to the second voltage from the hostdevice; send a response signal for notifying that the switching ispossible to the host device, and thereafter set the command/responsesignal line and the data signal lines at a ground level; start, afterthe clock signal line is set at a ground level by the host device,processing for switching a voltage outputted by the regulator from thefirst voltage to the second voltage, apply, when detecting that avoltage other than the ground level is applied to the clock signal lineby the host device, the second voltage to the command/response signalline and the data signal lines, which had been set at the ground level,to indicate completion of the switching processing to the host device,and start transmission/reception of signals at the second voltage aftercompletion of the switching processing.
 2. The connectable deviceaccording to claim 1, further comprising a voltage comparison circuitthat detects whether or not the signal voltage of the clock signal lineis the second voltage, wherein, when the voltage comparison circuitdetects that the signal voltage of the clock signal line is the secondvoltage, the connectable device controller applies the second voltage tothe command/response signal line and the data signal lines, which hadbeen set at the ground level, and when the voltage comparison circuitdetects that the signal voltage is not the second voltage, theconnectable device controller continues the ground level for at leastthe data signal lines.
 3. The connectable device according to claim 1,further comprising a voltage comparison circuit that detects whether ornot the voltage outputted by the regulator is the second voltage,wherein, when the other voltage comparison circuit detects that thevoltage outputted by the regulator is the second voltage, theconnectable device controller applies the second voltage to thecommand/response signal line and the data signal lines, which had beenset at the ground level, and when the voltage comparison circuit detectsthat the voltage outputted by the regulator is not the second voltage,the connectable device controller continues the ground level for atleast the data signal lines.
 4. The connectable device according toclaim 1, comprising a non-volatile memory section.
 5. The connectabledevice according to claim 1, further comprising a protection diodebetween an input end of the interface and a power line that supplies thefirst voltage.
 6. A host device to which a connectable device isconnectable, comprising: an interface that can transmit a command signalvia a command/response signal line, transmit a clock signal via a clocksignal line, receive a response signal via the command/response signalline, and transmit and receive a data signal via data signal lines atany one signal voltage selected from a first voltage and a secondvoltage which is lower than the first voltage; a regulator that canoutput the first voltage and the second voltage; and a host controlsection, the host control section configured to: send a command signalrequesting a switching processing for switching the signal voltage tothe second voltage to the connectable device, when switching the signalvoltage from the first voltage to the second voltage; receive a responsesignal from the connectable device, and thereafter set, when thecommand/response signal line is at the ground level, the clock signalline at a ground level, and then start processing for switching avoltage outputted by the regulator from the first voltage to the secondvoltage to switch the voltage to the second voltage within apredetermined time; supply the clock signal of the second voltage to theclock signal line after a predetermined time has elapsed since thesetting of the clock signal line at the ground level in the switchingprocessing; and start transmission/reception of signals at the secondvoltage, when detecting that the data signal lines are not at the groundlevel.
 7. The host device according to claim 6, wherein if an erroroccurs in the middle of the processing for switching the voltage, whenthe command/response signal line is at a level other than the groundlevel after receiving the response signal or when one of the data signallines is at the ground level after a predetermined time has elapsedsince supplying the clock signal of the second voltage, the host controlsection executes initialization processing in a first voltage mode. 8.The host device according to claim 6, further comprising: a voltagecomparison circuit that detects whether or not a signal voltage of thecommand/response signal line is the second voltage, wherein, after thehost control section supplies the clock signal of the second voltage tothe clock signal line, when the voltage comparison circuit detects thatthe signal voltage of the command/response signal line is the secondvoltage, the host control section starts transmission/reception ofsignals at the second voltage, and when the voltage comparison circuitdetects that the signal voltage of the command/response signal line isnot the second voltage, the host control section executes initializationprocessing in a first voltage mode.
 9. The host device according toclaim 6, wherein the connectable device comprises a non-volatile memorysection.
 10. The host device according to claim 6, further comprising aprotection diode between an input end of the interface and a power linethat supplies the first voltage.
 11. A system comprising: a host device;and a connectable device which is connectable to the host device, theconnectable device comprising: an interface that can receive a commandsignal via a command/response signal line, receive a clock signal via aclock signal line, transmit a response signal via the command/responsesignal line, and transmit and receive a data signal via data signallines at any one signal voltage selected from a first voltage and asecond voltage which is lower than the first voltage; and a firstregulator that can output the first voltage and the second voltage, thehost device comprising: an interface that can transmit the commandsignal via the command/response signal line, transmit the clock signalvia the clock signal line, receive the response signal via thecommand/response signal line, and transmit and receive the data signalvia the data signal lines at any one signal voltage selected from thefirst voltage and the second voltage; and a second regulator that canoutput the first voltage and the second voltage, wherein, when switchingof the signal voltage from the first voltage to the second voltage isperformed, the host device transmits the command signal requestingswitching of the signal voltage to the connectable device, and theconnectable device sends a response signal for notifying that theswitching is possible to the host device, and thereafter set thecommand/response signal line and data signal lines at a ground level,and wherein, when the connectable device can switch the signal voltage,after the clock signal is set at a ground level by the host device, theconnectable device and the host device start processing for switchingvoltages outputted by the first regulator and the second regulator fromthe first voltage to the second voltage, the host device supplies, aftera predetermined time has elapsed since the setting of the clock signalline at the ground level, the clock signal of the second voltage to theclock signal line, the connectable device applies, when detecting that avoltage other than the ground level is applied to the clock signal line,the second voltage to the command/response signal line and the datasignal lines, which had been set at the ground level, and the hostdevice starts transmission/reception of signals at the second voltage,after detecting that the data signal lines are not at the ground level.12. The system according to claim 11, wherein the connectable devicefurther comprises a first voltage comparison circuit that detectswhether or not the signal voltage of the clock signal line is the secondvoltage and a second voltage comparison circuit that detects whether ornot the voltage outputted by the first regulator is the second voltage,and the connectable device applies, when all the voltage comparisoncircuits detect that each of the voltages is the second voltage, thesecond voltage to the command/response signal line and the data signallines, which had been set at the ground level, and continues, when anyone of the voltage comparison circuits detects that the voltage is notthe second voltage, the ground level for at least the data signal lines,and the host device starts transmission/reception of signals at thesecond voltage when detecting that the data signal lines are not at theground level.
 13. The system according to claim 11, wherein theconnectable device comprises a non-volatile memory section.
 14. Thesystem according to claim 11, further comprising protection diodes, afirst one of which is provided between a host input end of the interfaceand a power line that supplies the first voltage and a second one ofwhich is provided between a device input end of the interface and apower line of the device that supplies the first voltage.
 15. A memorystorage device connectable to a host device comprising: a memory thatstores data; a memory controller that controls the memory; an interfacethat receives a command signal from the host device via a first signalline, the command signal requesting switching of a signal voltage foroperation of writing or reading of the data, receives a clock signalfrom the host device via a second signal line, transmits either one of afirst response signal or a second response signal to the host device viathe first signal line, receives data signals from the host device tostore data in the memory via third signal lines, and transmits datasignals corresponding to the data stored in the memory via the thirdsignal lines, the receiving and transmitting of the data signal beingperformed at the signal voltage of a first voltage or a second voltagewhich is lower than the first voltage; and a regulator that outputs thefirst voltage and the second voltage; wherein after receiving thecommand signal, the memory controller sends to the host device the firstresponse signal to operate the writing or reading of the data at thefirst voltage when the switching is not possible and sends to the hostdevice the second response signal for handshake processing to operatethe writing or reading of the data at the second voltage when theswitching is possible.
 16. The memory storage device according to claim15, wherein when the switching is possible, the memory controller setsthe first signal line and the third signal lines at a ground level,starts processing for the switching of the signal voltage outputted bythe regulator, applies the switched signal voltage to the first signalline and the third signal lines, which had been set at the ground level,to indicate completion of the switching of the signal voltage to thehost device, and starts transmission or reception of the data signals atthe switched signal voltage.
 17. The memory storage device according toclaim 15, wherein the operation of writing or reading of data isperformed with a normal speed or a high speed.
 18. The memory storagedevice according to claim 15, wherein the first response signal is toperform initializing processing and the second response signal is toperform handshake processing.
 19. The memory storage device according toclaim 15, wherein the memory storage device is configured to: start theprocessing for the switching of the signal voltage after the secondsignal line is set at the ground level by the host device, apply theswitched signal voltage to the first signal line and the third signallines, which had been set at the ground level, when detecting that avoltage other than the ground level is applied to the second signal lineby the host device, and start transmission or reception of the datasignals at the switched signal voltage after completion of theprocessing for the switching of the signal voltage.
 20. The memorystorage device according to claim 15, further comprising a voltagecomparison circuit that detects whether or not a voltage of the secondsignal line is the switched signal voltage, wherein, when the voltagecomparison circuit detects that the voltage of the second signal line isthe switched signal voltage, the memory controller applies the switchedsignal voltage to the first signal line and the third signal lines,which had been set at the ground level, and when the voltage comparisoncircuit detects that the voltage of the second signal line is not theswitched signal voltage, the memory controller continues the groundlevel for at least the third signal lines.
 21. The memory storage deviceaccording to claim 15, further comprising a voltage comparison circuitthat detects whether or not a voltage outputted by the regulator is theswitched signal voltage, wherein, when the voltage comparison circuitdetects that the voltage outputted by the regulator is the switchedsignal voltage, the memory controller applies the switched signalvoltage to the first signal line and the third signal lines. which hadbeen set at the ground level, and when the voltage comparison circuitdetects that the voltage outputted by the regulator is not the switchedsignal voltage, the memory controller continues the ground level for atleast the third signal lines.
 22. The memory storage device according toclaim 15, further comprising a non-volatile memory section.
 23. Thememory storage device according to claim 15, further comprising aprotection diode between an input end of the interface and a power linethat supplies the first voltage.